During the manufacture of semiconductor devices, such as integrated circuits, inspection operations are conducted to ensure that the product being produced conforms to the quality standards of the manufacturer. Defects, alignment tolerances, and surface irregularities are just a few of the characteristics of a printed circuit which are inspected. As the printed circuit is fabricated, it moves through various assembly stages. During assembly, inspections occur to ensure that features on the printed circuit (for example, bonding strips) are suitable for wire bonding.
Bonding strips are metallization surfaces on a printed circuit, or a chip carrier. The metallizations include conductors, voltage planes, ground planes, pads, and surface lands. The metallizations are used to electrically connect components to each other. Typically, a chip carrier has voltage and ground rings completely encircling a die. Wire leads from the die are connected to the voltage and ground rings by wire bonding. In a typical application, a die or chip may have hundreds of leads that need to be connected. Once the leads on the chip have been wire bonded, the chip may be packaged, often in plastic or ceramic, to form an integrated circuit device.
FIG. 1 depicts a die 18 attached to a conventional chip carrier 10. The die 18 has an array of terminal pads 20 for various input-output or "I/O" signals. Hundreds of terminal pads 20 are typical around the circumference of the die 18. Also shown are two bonding strips 12 and 14 surrounding the die 18. The bonding strips 12 and 14 are metallic strips deposited on the chip carrier 10, typically formed from copper or gold plating. Each bonding strip 12 and 14 has a predetermined voltage reference: for example, bonding strip 12 may carry a positive voltage reference and bonding strip 14 may carry a ground voltage reference. Leads 16, which are attached by soldering, connect I/O pads 20 to bonding strips 12 and 14.
Although there are typically hundreds of I/O leads 16 branching out from the die 18, most of the surface areas of the metallic bonding strips 12 and 14 are not used. In a typical application, only 35% to 40% of each metallic bonding strip 12 and 14 is used; therefore, most of the surface area of each bonding strip 12 and 14 is non-functional. Nevertheless, before assembly of the chip carrier 10 with the die 18, the entirety of each bonding strip 12 and 14 must be inspected for defects.
Any defects, such as scratches, pits, stains, or debris contamination, on the bonding strips 12 and 14 will result in rejection of the chip carrier 10. Because the inspector does not know which areas on the bonding strips 12 and 14 are functional and which areas are non-functional, a defect anywhere on the bonding strips 12 and 14 will cause a blanket rejection of the chip carrier 10. Inspection of an entire bonding strip 12, 14 is time consuming, and a blanket rejection of the chip carrier 10 is economically inefficient. Accordingly, it is desirable to provide a cost-effective structure on the chip carrier 10 that may help the inspector in deciding whether a defect on a metallic bonding strip 12, 14 is critical or not critical.
Structures, such as templates, are known for easing inspection of a semiconductor device. One example of a template is disclosed in U.S. Pat. No. 5,566,877 issued to McCormack. McCormack teaches a method for inspection by using a template image overlayed on top of a semiconductor device. The template image includes transparent regions and opaque regions. The opaque regions block out all areas of the device not associated with the characteristic being inspected, while the transparent regions highlight the area of interest. Using the superimposed image, the inspector can quickly focus on the area of the device requiring attention.
Another example of a template is disclosed by Frederick in U.S. Pat. No. 5,060,389. Frederick teaches a template adapted for placement in and removal from an optical tube of a microscope. The template is a transparent film selectively patterned by photographic methods from information contained in the manufacturer's database of die and package outlines and dimensions. By combining the image of the semiconductor device with the image of the template, an instantaneous determination of correct size, orientation, and placement can be made.
Yet another example of a template is provided in an article by Abbott et al. titled "Templates for Substrate Inspections," IBM Technical Disclosure Bulletin, Vol. 25, No. 12, page 6350, published May 1983. Abbott et al. disclose an overlay on a substrate for covering non-functional areas. The overlay is transparent over functional areas.
The templates discussed above are overlay structures and are not part of the semiconductor device itself. That is, the template may be placed on the semiconductor device during inspection, but may also be removed from the device after inspection. Another type of template, which is a structure built into the semiconductor device, has been disclosed in European Patent Application No. 0 285 820, published Dec. 10, 1988. This publication teaches a semiconductor device that includes terminal pads having two different shapes. The terminal pads that are functional are patterned into a square shape, and the terminal pads that are non-functional are patterned into a triangular shape. Because the final passivation layer that is deposited over the pad metal level of the semiconductor chip is transparent, the two shapes of the terminal pads may be distinguished during inspection. This facilitates inspection of solder balls fabricated on the terminal pads, because rework of defective solder balls on non-functional pads may be avoided.
The deficiencies of the conventional bonding strips formed on printed circuit boards or chip carriers and of the conventional methods for inspecting such bonding strips show that a need still exists. To overcome the shortcomings of the conventional devices and methods, a new structure and method are provided. An object of the present invention is to provide a structure that permits inspection of selective surface areas of the bonding strip. A related object is to reduce the inspection time of each bonding strip. Another object is to substantially eliminate unnecessary and costly rejections of printed circuit boards or chip carriers.